TPS40425_15 Datasheet, PDF (21/95 Pages) Texas Instruments – TPS40425 Dual Output, 2-Phase, Stackable PMBus™ Synchronous Buck Driverless Controller with Adaptive Voltage Scaling (AVS) Bus

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CS1P
CS1N
CS2P
CS2N
TPS40425
SLUSBO6A – JANUARY 2014 – REVISED JULY 2014
+
Current Sharing
Block

I_SH_Bus
COMP_Bus
+
Current Sharing
Block

PWM1
+
PWM2
+
Device 1
CS1P
+
Current Sharing
Block

CS1N
I_SH_Bus
CS2P
+
CS2N
Current Sharing
Block

NOTE: All the current sharing components are integrated in the device.
Figure 17. Current Sharing
PWM1
+
PWM2
+
Device 2
7.3.10 Linear Regulators
The TPS40425 device has two on-board linear regulators that provide suitable power for the internal circuitry of
the device. These pins, BP3 and BP5 must be properly bypassed to function properly. The BP3 pin requires a
minimum capacitance of 0.33 µF connected to AGND and the BP5 pin should have approximately 1 μF of
capacitance connected to PGND. The bypass capacitors for VDD, BP5 and BP3 pins need to be placed as close
to the device as possible.
7.3.11 Power Sequence Between TPS40425 Device and Power Stage
Before soft-start operation begins to generate a PWM signal, the VDD voltage for power stage must be prepared.
Please refer to the power stage datasheet for VDD value. Without preparation, the TPS40425 device outputs the
PWM signal at maximum duty cycle, because the power stage is not working and output voltage is not regulated.
The VDD voltage for power stage needs to be above its threshold until TPS40425 device is turned off.
7.3.12 PWM Signal
The PWM signal has three voltage levels:
• High level to turn on only the high-side MOSFET
• Level level to turn on only the low-side MOSFET
• Tri-state level to turn off both high-side and low-side MOSFETs
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