TMS320F28027 Datasheet, PDF (21/130 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com
SPRS523F – NOVEMBER 2008 – REVISED DECEMBER 2010
Table 3-4. Impact of Using the Code Security Module
ADDRESS
0x3F 7F80 – 0x3F 7FEF
0x3F 7FF0 – 0x3F 7FF5
CODE SECURITY ENABLED
Fill with 0x0000
FLASH
CODE SECURITY DISABLED
Application code and data
Reserved for data only
Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read
peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as
written. Because of the pipeline, a write immediately followed by a read to different memory locations, will
appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The CPU supports a block
protection mode where a region of memory can be protected so that operations occur as written (the
penalty is extra cycles are added to align the operations). This mode is programmable and by default, it
protects the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-5 .
AREA
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
Peripheral Frame 2
L0 SARAM
OTP
FLASH
FLASH Password
Boot-ROM
Table 3-5. Wait-states
WAIT-STATES (CPU)
0-wait
0-wait
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait data and program
Programmable
1-wait minimum
Programmable
0-wait Paged min
1-wait Random min
Random ≥ Paged
16-wait fixed
0-wait
Fixed
COMMENTS
Cycles can be extended by peripheral generated ready.
Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Fixed. Cycles cannot be extended by the peripheral.
Assumes no CPU conflicts
Programmed via the Flash registers.
1-wait is minimum number of wait states allowed.
Programmed via the Flash registers.
Wait states of password locations are fixed.
Copyright © 2008–2010, Texas Instruments Incorporated
Functional Overview
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