TLV320AIC29 Datasheet, PDF (21/85 Pages) Texas Instruments – STWREO AUDIO CODEC WITH INTERGRATED HEADPHONE AND SPEAKER AMPLIFIERS

TLV320AIC29
www.ti.com
SLAS494A − DECEMBER 2005 − REVISED JANUARY 2006
D Left Justified Mode
In left-justified mode, the MSB of right channel is valid on the rising edge of BCLK, following the falling edge on
WCLK. Similarly the MSB of left channel is valid on the rising edge of BCLK following the rising edge of
WCLK.
1/fs
WCLK
BCLK
SDIN/
SDOUT
Left Channel
n n−1 n−2
MSB
210
LSB
Right Channel
n n−1 n−2
210
n n−1
Figure 16. Timing Diagram for Left-Justified Mode
D I²S Mode
In I²S mode, the MSB of left channel is valid on the second rising edge of BCLK, after the falling edge on
WCLK. Similarly the MSB of right channel is valid on the second rising edge of BCLK, after the rising edge of
WCLK.
1/fs
WCLK
BCLK
1 clock before MSB
Left Channel
Right Channel
SDIN/
SDOUT
n n−1 n−2
210
n n−1 n−2
210
n
MSB
LSB
Figure 17. Timing Diagram for I2S Mode
D DSP Mode
In DSP mode, the falling edge of WCLK starts the data transfer with the left channel data first and immediately
followed by the right channel data. Each data bit is valid on the falling edge of BCLK.
1/fs
WCLK
BCLK
Left Channel
Right Channel
SDIN/
SDOUT ^{1 0 n n−1 n−2}
2 1 0 n n−1 n−2
2 1 0 n n−1 n−2
LSB MSB
LSB MSB
LSB MSB
Figure 18. Timing Diagram for DSP Mode
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