TFP501 Datasheet, PDF (21/24 Pages) Texas Instruments – PANELBUS HDCP DIGITAL RECEIVER

I²C interface (continued)
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
S Slave Address W A Sub Address A Sr Slave Address R A Data A Data A P
From Transmitter
From Receiver
A Acknowledge
S Start Condition
P Stop Condition
Sr Restart Condition
W Write
R Read
A Not Acknowledge (SDA High)
Figure 19. I²C Read Cycle
S Slave Address R A
Data
A
Data
AP
From Transmitter
From Receiver
A Acknowledge
S Start Condition
P Stop Condition
R Read
A Not Acknowledge (SDA High)
Figure 20. HDCP Port Link Integrity Message Read
PowerPAD 100-pin TQFP package
The TFP501 is packaged in TI’s thermally enhanced PowerPAD 100-pin TQFP packaging. The PowerPAD
package is a 14 mm × 14 mm × 1 mm TQFP outline with 0.5mm lead-pitch. The PowerPAD package has a
specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the
same outline. The TI 100-pin TQFP PowerPAD package offers a backside solder plane that connects directly
to the die mount pad for enhanced thermal conduction. Soldering the backside of the TFP501 to the application
board is not required thermally, as the device power dissipation is well within the package capability when not
soldered.
Soldering the backside of the device to the PCB ground plane is recommended for electrical considerations.
Since the die pad is electrically connected to the chip substrate and hence chip ground, connection of the
PowerPAD back side to a PCB ground plane helps to improve EMI, ground bounce, and power supply noise
performance.
The following table outlines the thermal properties of the TI 100-pin TQFP PowerPAD package. The 100-pin
TQFP non-PowerPAD package is included only for reference.
Table 1. TI 100-Pin TQFP (14 × 14 × 1 mm)/0.5 mm Lead Pitch
PARAMETER
WITHOUT
PowerPAD
PowerPAD
NOT CONNECTED
TO PCB THERMAL
PLANE
PowerPAD
CONNECTED TO PCB
THERMAL PLANE
(see Note 14)
R_θJA Junction-to-ambient thermal resistance (see Notes 14 and 15)
49.17°C/W
27.32°C/W
17.28°C/W
R_θJC Junction-to-case thermal resistance (see Notes 14 and 15)
3.11°C/W
0.12°C/W
0.12°C/W
PD Package power dissipation (see Notes 14, 15 and 16)
1.6 W
2.9 W
4.6 W
NOTES: 15. Specified with the PowerPAD bond pad on the backside of the package soldered to a 2 oz Cu plate PCB thermal plane.
16. Airflow is at 0 LFM (no airflow).
17. Specified at 150°C junction temperature and 70°C ambient temperature.
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