SN74VMEH22501 Datasheet, PDF (21/25 Pages) Texas Instruments – 8 BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1 BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT FEEDBACK PATH AND 3 STATE OUTPUTS

SN74VMEH22501
8ĆBIT UNIVERSAL BUS TRANSCEIVER AND TWO 1ĆBIT BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3ĆSTATE OUTPUTS
SCES357E − JULY 2001 − REVISED MARCH 2004
VMEbus SUMMARY
In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications. The
data-transfer protocols used to define the VMEbus came from the Motorola VERSA bus architecture that owed its
heritage to the then recently introduced Motorola 68000 microprocessor. The VMEbus, when introduced, defined two
basic data-transfer operations: single-cycle transfers consisting of an address and a data transfer, and a block
transfer (BLT) consisting of an address and a sequence of data transfers. These transfers were asynchronous, using
a master-slave handshake. The master puts address and data on the bus and waits for an acknowledgment. The
selected slave either reads or writes data to or from the bus, then provides a data-acknowledge (DTACK*) signal. The
VMEbus system data throughput was 40 Mbyte/s. Previous to the VMEbus, it was not uncommon for the backplane
buses to require elaborate calculations to determine loading and drive current for interface design. This approach
made designs difficult and caused compatibility problems among manufacturers. To make interface design easier
and to ensure compatibility, the developers of the VMEbus architecture defined specific delays based on a 21-slot
terminated backplane and mandated the use of certain high-current TTL drivers, receivers, and transceivers.
In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby doubling
the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the double-edge transfer
(2eVME) protocol, doubling the data rate again. In 1997, the VMEbus International Trade Association (VITA)
established a task group to specify a synchronous protocol to increase data-transfer rates to 320 Mbyte/s, or more.
The unreleased specification, VITA 1.5 [double-edge source synchronous transfer (2eSST)], is based on the
asynchronous 2eVME protocol. It does not wait for acknowledgement of the data by the receiver and requires
incident-wave switching. Sustained data rates of 1 Gbyte/s, more than ten times faster than traditional VME64
backplanes, are possible by taking advantage of 2eSST and the 21-slot VME320 star-configuration backplane. The
VME320 backplane approximates a lumped load, allowing substantially higher-frequency operation over the VME64x
distributed-load backplane. Traditional VME64 backplanes with no changes theoretically can sustain 320 Mbyte/s.
From BLT to 2eSST − A Look at the Evolution of VMEbus Protocols by John Rynearson, Technical Director, VITA,
provides additional information on VMEbus and can be obtained at www.vita.com.
maximum data transfer rates
DATE
1981
1989
1995
1997
1999
TOPOLOGY
VMEbus IEEE-1014
VME64
VME64x
VME64x
VME320
PROTOCOL
BLT
MBLT
2eVME
2eSST
2eSST
DATA BITS
PER CYCLE
32
64
64
64
64
DATA TRANSFERS
PER CLOCK CYCLE
1
1
2
2-No Ack
2-No Ack
PER SYSTEM
(Mbyte/s)
40
80
160
160−320
320−1000
FREQUENCY (MHz)
BACKPLANE CLOCK
10
10
10
10
10
20
10−20
20−40
20−62.5
40−125
applicability
Target applications for VME backplanes include industrial controls, telecommunications, simulation,
high-energy physics, office automation, and instrumentation systems.
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