LM3S9L97 Datasheet, PDF (209/1219 Pages) Texas Instruments – Stellaris® LM3S9L97 Microcontroller

Stellaris® LM3S9L97 Microcontroller
7.3.1
7.3.2
Power-up from a power cut to code execution is defined as the regulator turn-on time (specified at
t_{HIB_TO_VDD} maximum) plus the normal chip POR (see “Hibernation Module” on page 1153).
Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is t_{HIB_REG_ACCESS}, therefore
software must guarantee that this delay is inserted between back-to-back writes to certain Hibernation
registers or between a write followed by a read to those same registers. The timing for back-to-back
reads from the Hibernation module has no restrictions. Software may make use of the WRC bit in
the Hibernation Control (HIBCTL) register to ensure that the required timing gap has elapsed.
This bit is cleared on a write operation and set once the write completes, indicating to software that
another write or read may be started safely. Software should poll HIBCTL for WRC=1 prior to accessing
any affected register. The following registers are subject to this timing restriction:
■ Hibernation RTC Counter (HIBRTCC)
■ Hibernation RTC Match 0 (HIBRTCM0)
■ Hibernation RTC Match 1 (HIBRTCM1)
■ Hibernation RTC Load (HIBRTCLD)
■ Hibernation RTC Trim (HIBRTCT)
■ Hibernation Data (HIBDATA)
Hibernation Clock Source
In systems where the Hibernation module is used to put the microcontroller into hibernation, the
module must be clocked by an external source that is independent from the main system clock,
even if the RTC feature is not used. An external oscillator or crystal is used for this purpose. To use
a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is
divided by 128 internally to produce a 32.768-kHz Hibernation clock reference. Alternatively, a
32.768-kHz oscillator can be connected to the XOSC0 pin, leaving XOSC1 unconnected. Care must
be taken that the voltage amplitude of the 32-kHz oscillator is less than V_BAT, otherwise, the
Hibernation module draws power from the oscillator and not V_BAT during hibernation. See Figure
7-2 on page 210 and Figure 7-3 on page 210. Note that these diagrams only show the connection to
the Hibernation pins and not to the full system. See “Hibernation Module” on page 1153 for specific
values.
The Hibernation clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The
type of clock source is selected by clearing the CLKSEL bit for a 4.194304-MHz crystal and setting
the CLKSEL bit for a 32.768-kHz oscillator. If a crystal is used for the clock source, the software
must leave a delay of t_{XOSC_SETTLE} after writing to the CLK32EN bit and before any other accesses
to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an
oscillator is used for the clock source, no delay is needed.
June 15, 2010
209
Texas Instruments-Advance Information