TPS62620 Datasheet, PDF (20/28 Pages) Texas Instruments – 600-mA, 6-MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER IN CHIP SCALE PACKAGING

TPS62620, TPS62621
TPS62622, TPS62623
TPS62624, TPS62625
SLVS848A – JULY 2009 – REVISED JULY 2009 ............................................................................................................................................................... www.ti.com
OUTPUT CAPACITOR SELECTION
The advanced fast-response voltage mode control scheme of the TPS6262x allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. For best performance, the device should be operated with a minimum effective output
capacitance of 1.6µF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor
impedance.
At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load
transitions. A 4.7µF capacitor typically provides sufficient bulk capacitance to stabilize the output during large
load transitions. The typical output voltage ripple is 1% of the nominal output voltage V_O.
The output voltage ripple during PFM mode operation can be kept very small. The PFM pulse is time controlled,
which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting
PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the
inductor value. The PFM frequency decreases with smaller inductor values and increases with larger once.
Increasing the output capacitor value and the effective inductance will minimize the output ripple voltage.
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 2.2-µF capacitor is sufficient.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between C_I and the power source lead to reduce ringing than can occur between the inductance of the power
source leads and C_I.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, I_L
• Output ripple voltage, V_O(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. V_O immediately shifts by an amount equal to ΔI_(LOAD) x ESR, where ESR
is the effective series resistance of C_O. ΔI_(LOAD) begins to charge or discharge C_O generating a feedback error
signal used by the regulator to return V_O to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, V_O can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
r_DS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
load current range, and temperature range.
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