TPS54541_15 Datasheet, PDF (20/52 Pages) Texas Instruments – TPS54541 4.5-V to 42-V Input, 5-A Step-Down DC-DC Converter With Soft-Start and Eco-mode™

TPS54541
SLVSC57A – OCTOBER 2013 – REVISED AUGUST 2015
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Feature Description (continued)
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54541 device is adjustable over a wide range from 100 to 2500 kHz by
placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 10 or Equation 11 or the curves in Figure 5 and Figure 6. To reduce the solution size
typically set the switching frequency as high as possible. Consider the tradeoffs of the conversion efficiency,
maximum input voltage, and minimum controllable on time. The minimum controllable on time is typically 135 ns,
which limits the maximum operating frequency in applications with high input to output step-down ratios. The
maximum switching frequency is also limited by the frequency-foldback circuit. A more detailed discussion of the
maximum switching frequency is provided in the next section.
RT
(kW)
=
92 417
ƒ_SW (kHz)^0.991
(10)
ƒ_SW
(kHz) =
101756
RT (kW)^1.008
(11)
7.3.11 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature, connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 37. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2.0 V and
have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 to 2300 kHz. The rising edge
of the SW synchronizes to the falling edge of RT/CLK pin signal. Design the external synchronization circuit such
that the default-frequency set resistor connects from the RT/CLK pin to ground when the synchronization signal
is off. When using a low impedance signal source, the frequency set resistor connects in parallel with an AC-
coupling capacitor to a termination resistor (for example, 50 Ω) as shown in Figure 37. The two resistors in the
series provide the default-frequency-setting resistance when the signal source is turned off. The sum of the
resistance sets the switching frequency close to the external CLK frequency. AC-coupling the synchronization
signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended.
The first time the RT/CLK is pulled above the PLL threshold, the TPS54541 device switches from the RT-resistor
free-running frequency mode to the PLL-synchronized mode. The internal 0.5-V voltage source is removed and
the RT/CLK pin becomes high impedance as the PLL begins to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 µs. During the transition
from the PLL mode to the resistor programmed mode, the switching frequency falls to 150 kHz and then
increases or decreases to the resistor programmed frequency when the 0.5-V bias voltage is reapplied to the
RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device
implements a digital frequency foldback enables synchronization to an external clock during normal startup and
fault conditions. Figure 38, Figure 39 and Figure 40 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
SPACER
Clock
Source
RT/CLK
RT
TPS54541
PLL
RT/CLK
Hi-Z
Clock
RT
Source
TPS54541
PLL
Figure 37. Synchronizing to a System Clock
20
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