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TMS370CX1X Datasheet, PDF (20/50 Pages) Texas Instruments – 8-BIT MICROCONTROLLER | |||
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TMS370Cx1x
8-BIT MICROCONTROLLER
SPNS012F â MAY 1987 â REVISED FEBRUARY 1997
programmable timer 1 (continued)
Table 15. Timer 1 Module Register Memory Map
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ PF BIT7
BIT 6
BIT 5
BIT 4
BIT 3
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Modes: Dual-Compare and Capture/Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P040 Bit15
T1Counter MSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P041 Bit7
T1 Counter LSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P042 Bit15
Compare Register MSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P043 Bit7
Compare Register LSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P044 Bit15
Capture/Compare Register MSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P045 Bit7
Capture/Compare Register LSbyte
P046 Bit 15
Watchdog Counter MSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P047 Bit7
Watchdog Counter LSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P048 Bit7
Watchdog Reset Key
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P049
WD OVRFL
TAP SELâ
WD INPUT
SELECT2â
WD INPUT
SELECT1â
WD INPUT
SELECT0â
â
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04A
WD OVRFL
RST ENAâ
WD OVRFL
INT ENA
WD OVRFL
INT FLAG
T1 OVRFL
INT ENA
T1 OVRFL
INT FLAG
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Mode: Dual-Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04B
T1EDGE
INT FLAG
T1C2
INT FLAG
T1C1
INT FLAG
â
â
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04C
T1
MODE=0
T1C1
T1C2
OUT ENA OUT ENA
T1C1
RST ENA
T1CR
OUT ENA
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Mode: Capture/Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04B
T1EDGE
INT FLAG
â
T1C1
INT FLAG
â
â
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ T1
T1C1
T1C1
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04C MODE=1 OUTENA
â
RST ENA
â
Modes: Dual-Compare and Capture / Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04D
â
â
â
â
T1EVT
DATA IN
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04E
T1PWM
DATA IN
T1PWM
T1PWM
T1PWM
DATA OUT FUNCTION DATA DIR
T1IC/CR
DATA IN
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04F T1STEST
T1
PRIORITY
â
â
â
BIT 2
BIT 1
T1 INPUT
SELECT2
â
T1 INPUT
SELECT1
â
T1EDGE
INT ENA
T1EDGE
POLARITY
T1C2
INT ENA
T1CR
RST ENA
T1EDGE
INT ENA
â
T1EDGE
POLARITY
â
T1EVT
DATA OUT
T1IC/CR
DATA OUT
T1EVT
FUNCTION
T1IC/CR
FUNCTION
â
â
BIT 0
REG
Bit 8 T1CNTR
Bit 0
Bit 8 T1C
Bit 0
Bit 8 T1CC
Bit 0
Bit 8 WDCNTR
Bit 0
Bit 0 WDRST
T1 INPUT
SELECT0
T1CTL1
T1
SW RESET
T1CTL2
T1C1
INT ENA
T1EDGE
DET ENA
T1CTL3
T1CTL4
T1C1
INT ENA
T1EDGE
DET ENA
T1CTL3
T1CTL4
T1EVT
DATA DIR
T1IC/CR
DATA DIR
â
T1PC1
T1PC2
T1PRI
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ â Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.
20
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