THS770012_15 Datasheet, PDF (20/35 Pages) Texas Instruments – Broadband, Fully-Differential, 14-/16-Bit ADC Driver Amplifier

THS770012
SLOS669C – FEBRUARY 2010 – REVISED JANUARY 2012
www.ti.com
Operation with Split Supply ±2.5V
The THS770012 can be operated using a split ±2.5V supply. In this case, V_S+ is connected to +2.5V, and GND
(and any other pin noted to be connected to GND) is connected to -2.5V. As with any device, the THS770012 is
impervious to what the user decides to name the levels in the system. In essence, it is simply a level shift of the
power pins by –2.5V. If everything else is level-shifted by the same amount, the device sees no difference. With
a ±2.5V power supply, the V_OCM range is 0V ±0.25V; therefore, power-down levels are –2.5V = on and +2.5V =
off, and input and output voltage ranges are symmetrical about 0V. This design has certain advantages in
systems where signals are referenced to ground, and as noted in the following section, for driving ADCs with low
input common-mode voltage requirements in dc-coupled applications.
Driving Capcitive Loads
The THS770012 is tested as described previously, with the data shown in the typical graphs. Due to the internal
gain resistor architecture used on the device, the only practical means to avoid stability problems such as
overshoot/ringing, gain peaking, and oscillation when driving capacitive loads is to place small resistors in series
with the outputs (R_O) to isolate the phase shift caused by the capacitive load from the feedback loop of the
amplifier. Note there are 2Ω internal resistors in series with each output to help maintain stability. The Typical
Characteristics graphs show recommended values for an optimally flat frequency response with maximum
bandwidth. Smaller values of R_O can be used if more peaking is allowed, and larger values can be used to -
reduce the bandwidth.
Driving ADCs
The THS770012 is designed and optimized for the highest performance to drive differential input ADCs.
Figure 40 shows a generic block diagram of the THS770012 driving an ADC. The primary interface circuit
between the amplifier and the ADC is usually a filter of some type for antialias purposes, and provides a means
to bias the signal to the input common-mode voltage required by the ADC. Filters range from single-order real
RC poles to higher-order LC filters, depending on the requirements of the application. Output resistors (R_O) are
shown on the amplifier outputs to isolate the amplifier from any capacitive loading presented by the filter.
V_IN-
V_IN+
V_OCM
50W
50W
THS770012
200W
V_OCM
200W
V_OUT+
R_O
V_OUT-
R_O
Filter
and
Bias
A_IN+
ADC
A_{IN- CM}
Figure 40. Generic ADC Driver Block Diagram
The key points to consider for implementation are described in the following three subsections.
SNR Considerations
The signal-to-noise ratio (SNR) of the amplifier + filter + ADC adds in RMS fashion. Noise from the amplifier is
bandwidth-limited by the filter. Depending on the amplitude of the signal and the bandwidth of the filter, the SNR
of the amplifier + filter can be calculated. To get the combined SNR, this value is then squared, added to the
square of the ADC SNR, and the square-root is taken. If the SNR of the amplifier + filter equals the SNR of the
ADC, the combined SNR is 3dB higher and for minimal inpact on the ADC's SNR the SNR of the amplifier + filter
should be 10dB or more lower. The combined SNR calculated in this manner is usually accurate to within ±1dB
of actual implementation.
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