SN54ABTH18504A Datasheet, PDF (20/35 Pages) Texas Instruments – SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input-mode I/O pins is compressed into a 20-bit parallel signature in the
shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, a 20-bit
pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on each
rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling
edge of TCK. Figures 9 and 10 show the 20-bit linear-feedback shift-register algorithms through which the
signature and patterns are generated. An initial seed value should be scanned into the BSR before performing
this operation. A seed value of all zeroes does not produce additional patterns.
A20-I/O A19-I/O A18-I/O A17-I/O A16-I/O A15-I/O A14-I/O A13-I/O A12-I/O A11-I/O
A10-I/O A9-I/O A8-I/O A7-I/O A6-I/O A5-I/O A4-I/O A3-I/O A2-I/O A1-I/O
=
=
B20-I/O B19-I/O B18-I/O B17-I/O B16-I/O B15-I/O B14-I/O B13-I/O B12-I/O B11-I/O
B10-I/O B9-I/O B8-I/O B7-I/O B6-I/O B5-I/O B4-I/O B3-I/O
Figure 9. 20-Bit PSA/PRPG Configuration (OEAB = 0, OEBA = 1)
B2-I/O
B1-I/O
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