PCM1691 Datasheet, PDF (20/47 Pages) Texas Instruments – 24-Bit, 192-kHz Sampling, Enhanced Multi-Level, ΔΣ,Eight-Channel, Audio Digital-to-Analog Converter

PCM1691
SBAS450 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com
AUDIO INTERFACE TIMING
Figure 29 and Table 6 describe the detailed audio interface timing specifications.
BCK
(Input)
LRCK
(Input)
t_BCH
t_BCL
t_BCY
t_LRH
t_LRS
1.4 V
1.4 V
t_DIS
t_DIH
DIN1/2/3/4
1.4 V
Figure 29. Audio Interface Timing Diagram for Left-Justified, Right-Justified, I²S, and DSP Data Formats
SYMBOL
t_BCY
t_BCH
t_BCL
t_LRS
t_LRH
t_DIS
t_DIH
Table 6. Timing Requirements for Figure 29
DESCRIPTION
BCK cycle time
BCK pulse width high
BCK pulse width low
LRCK setup time to BCK rising edge
LRCK hold time to BCK rising edge
DIN1/2/3/4 setup time to BCK rising edge
DIN1/2/3/4 hold time to BCK rising edge
MIN
TYP
75
35
35
10
10
10
10
BCK
(Input)
LRCK
(Input)
t_BCH
t_BCL
t_BCY
t_LRH
t_LRS
t_DIS
t_DIH
t_LRW
DIN1/2/3/4
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
1.4 V
1.4 V
1.4 V
Figure 30. Audio Interface Timing Requirements for DSP and TDM Data Formats
SYMBOL
t_BCY
t_BCH
t_BCL
t_LRW
t_LRS
t_LRH
t_DIS
t_DIH
Table 7. Timing Requirements for Figure 29
DESCRIPTION
BCK cycle time
BCK pulse width high
BCK pulse width low
LRCK pulse width high (DSP format)
LRCK pulse width high (TDM format)
LRCK setup time to BCK rising edge
LRCK hold time to BCK rising edge
DIN1/2/3/4 setup time to BCK rising edge
DIN1/2/3/4 hold time to BCK rising edge
MIN
TYP
40
15
15
t_BCY
t_BCY
10
10
10
10
MAX
t_BCY
1/f_S – t_BCY
UNIT
ns
ns
ns
sec
sec
ns
ns
ns
ns
20
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