CC2540F128 Datasheet, PDF (20/34 Pages) Texas Instruments – 2.4-GHz Bluetooth® low energy System-on-Chip

CC2540F128, CC2540F256
SWRS084C – OCTOBER 2010 – REVISED NOVEMBER 2011
www.ti.com
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2 is a 40-bit timer used by the Bluetooth low energy stack. It has a 16-bit counter with a configurable timer
period and a 24-bit overflow counter that can be used to keep track of the number of periods that have
transpired. A 40-bit capture register is also used to record the exact time at which a start-of-frame delimiter is
received/transmitted or the exact time at which transmission ends. There are two 16-bit timer-compare registers
and two 24-bit overflow-compare registers that can be used to give exact timing for start of RX or TX to the radio
or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free
for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead
of using some oversampling scheme, and are thus well-suited for high data rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,
respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The
inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a
single-ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can
automate the process of periodic sampling or conversion over a sequence of channels.
The operational amplifier is intended to provide front-end buffering and gain for the ADC. Both inputs as well as
the output are available on pins, so the feedback network is fully customizable. A chopper-stabilized mode is
available for applications that need good accuracy with high gain.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin
interrupt.
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