BQ25015 Datasheet, PDF (20/28 Pages) Texas Instruments – SINGLE-CHIP CHARGER AND DC/DC CONVERTER IC FOR PORTABLE APPLICATIONS

bq25015
bq25017
SLUS721A – DECEMBER 2006 – REVISED MARCH 2007
www.ti.com
where
T_J = chip junction temperature
T_A = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θ_JA include:
• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested
The device power dissipation (P) is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from the following equation:
ǒ Ǔ _{P + VIN * VIN(BAT) IOUT(OUT)}
(17)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest.
PCB LAYOUT CONSIDERATIONS
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and switching frequencies. If the layout is not carefully done the regulator could exhibit stability problems as well
as EMI problems. With this in mind, one should lay out the PCB using wide, short traces for the main current
paths. The input capacitor, as well as the inductor and output capacitors, should be placed as close as possible
to the IC pins.
The feedback resistor network must be routed away from the inductor and switch node to minimize noise and
magnetic interference. To further minimize noise from coupling into the feedback network and feedback pin, the
ground plane or ground traces must be used for shielding. This becomes very important especially at high
switching frequencies.
The following are some additional guidelines that should be observed:
• To obtain optimal performance, the decoupling capacitor from AC to VSS (and from USB to VSS) and the
output filter capacitors from BAT/OUT to VSS should be placed as close as possible to the bq25015/7, with
short trace runs to both signal and VSS pins.
• All low-current VSS connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
• The BAT/OUT pin provides voltage feedback to the IC for the charging function and should be connected
with its trace as close to the battery pack as possible.
• The high current charge paths into AC and USB and from the BAT/OUT and SW pins must be sized
appropriately for the maximum charge or output current in order to avoid voltage drops in these traces.
• The bq25015/7 deviecs are packaged in a thermally enhanced MLP package. The package includes a
thermal pad to provide an effective thermal contact between the IC and the printed circuit board (PCB). Full
PCB design guidelines for this package are provided in the application note QFN/SON PCB Attachment
(SLUA271).
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