ADS7891 Datasheet, PDF (20/31 Pages) Burr-Brown (TI) – 14BIT 3 MSPS LOW POWER SAR ANALOG TO DIGITAL CONVERTER

ADS7891
SLAS410 − DECEMBER 2003
PRINCIPLES OF OPERATION
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The ADS7891 is a member of a family of high-speed successive approximation register (SAR) analog-to-digital
converters (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold
function.
The conversion clock is generated internally. The conversion time is 273 ns max (at 5 V +VBD).
The analog input is provided to two input pins: +IN and −IN. (Note that this is pseudo differential input and there
are restrictions on –IN voltage range.) When a conversion is initiated, the difference voltage between these pins
is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from
any internal function.
REFERENCE
The ADS7891 has a built-in 2.5-V (nominal value) reference but can operate with an external reference. When
an internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1-µF decoupling
capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47, 48 (REFM). The internal
reference of the converter is buffered . There is also a buffer from REFIN to CDAC. This buffer provides isolation
between the external reference and the CDAC and also recharges the CDAC during conversion. It is essential
to decouple REFOUT to AGND with a 0.1-µF capacitor while the device operates with an external reference.
ANALOG INPUT
When the converter enters hold mode, the voltage difference between the +IN and −IN inputs is captured on
the internal capacitor array. The voltage on the −IN input is limited to between –0.2 V and 0.2 V, thus allowing
the input to reject a small signal which is common to both the +IN and −IN inputs. The +IN input has a range
of –0.2 V to (+V_ref +0.2 V). The input span (+IN – (−IN)) is limited from 0 V to VREF.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, signal
frequency, and source impedance. Essentially, the current into the ADS7891 charges the internal capacitor
array during the sample period. After this capacitance has been fully charged, there is no further input current
(this may not happen when a signal is moving continuously). The source of the analog input voltage must be
able to charge the input capacitance (27 pF) to better than a 14-bit settling level with a step input within the
acquisition time of the device. The step size can be selected equal to the maximum voltage difference between
two consecutive samples at the maximum signal frequency. (Refer to Figure 39 for the suggested input circuit.)
When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both
−IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter’s linearity may
not meet specifications.
Care should be taken to ensure that +IN and −IN see the same impedance to the respective sources. (For
example, both +IN and −IN are connected to a decoupling capacitor through a 21-Ω resistor as shown in
Figure 39.) If this is not observed, the two inputs could have different settling times. This may result in an offset
error, gain error, or linearity error which changes with temperature and input voltage.
RECOMMENDED OPERATIONAL AMPLIFIERS
It is recommended to use the THS4031 or THS4211 op amps for the analog input. All of the performance figures
in this data sheet are measured using the THS4031. Refer to Figure 39 for more information.
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