TRF1216_07 Datasheet, PDF (2/13 Pages) Texas Instruments – 3.5-GHz, HIGH DYNAMIC RANGE, LOW-NOISE DOWN-CONVERTER

TRF1216
SLWS172A – APRIL 2005 – REVISED DECEMBER 2005
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAM
The detailed block diagram and the pin-out of the ASIC are shown in Figure 1 and Table 1.
VDD1
VDD2 LNAO MXRI
VDDIF
LNAI
Dual Stage-LNA
Mixer
BALUN
VGA
IFB
IFOP
IFON
RFAGC
LO Buffer
LOP
LON
RFATTN
GND
VDDLO
Figure 1. Detailed Block Diagram of TRF1216
B0084-01
TERMINAL
I/O
NO.
NAME
1
LNAO O
2
VDD1
I
3, 4, 6, 9,
16, 19
GND
–
5
LNAI
I
7
LOP
I
8
LON
I
10
VDDLO I
11
IFB
–
12
VDDIF I
13
IFON O
14
IFOP O
15
RFAGC I
17
18
20
Back
RFATTN I
MXRI
I
VDD2 –
GND
–
TERMINAL FUNCTIONS
TYPE
DESCRIPTION
Analog
Power
–
Analog
Analog
Analog
Power
–
Power
Analog
Analog
Analog
Digital
Analog
Power
–
LNA Output, 50 Ω, ac-coupled
LNA1 DC Bias (+5 V nominal)
Ground
RF input – Needs dc block and input matching for optimum noise figure
LO input positive, ac coupled
LO input negative, ac coupled
LO DC Bias (+5 V nominal)
Not connected for normal operation. IF Bias Adjustment. Do not ground this pin or connect to any
other pin.
IF Bias Network dc Bias (+5 V nominal)
IF output and bias (see the application schematic for connections).
IF output and bias (see the application schematic for connections).
Input voltage for analog gain control V_RFAGC = 0 V to 1.5 V Max gain at V_RFAGC = 0 V Min gain at
V_RFAGC = 1.5 V
TTL control for switched attenuator TTL low – Attenuator switched in TTL high – Attenuator
switched out
Mixer Input 50 Ω
LNA2 dc bias (+5 V nominal)
Back of package has metal base that must be grounded for thermal and RF performance.
2