TPS40020 Datasheet, PDF (2/32 Pages) Texas Instruments – ENHANCED LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER

TPS40020
TPS40021
SLUS535C − MARCH 2003 − REVISED SEPTEMBER 2004
DESCRIPTION (CONTINUED)
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The short circuit current detection is programmable through a single resistor, allowing the short circuit current limit
detection threshold to be easily tailored to accommodate different size (R_DS(on)) MOSFETs. The short circuit current
function provides pulse-by-pulse current limiting during soft-start and short term transient conditions as well as a fault
counter to handle longer duration short circuit current conditions. If a fault is detected the controller shuts down for
a period of time determined by six (6) consecutive soft-start cycles. The controller automatically retries the output
every seventh (7^th) soft-start cycle.
In addition to determining the off time during a fault condition, the soft-start ramp provides a closed loop controlled
ramp of the converter output during startup. Programmability allows the ramp rate to be adjusted for a wide variety
of output L-C component values.
The output voltage transient comparators provide a quick response , first strike, approach to output voltage transients. The
output voltage is sensed through a resistor divider at the OSNS pin. If an overvoltage condition is detected the HDRV gate
drive is shut-off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output
undervoltage condition is sensed the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. In either
case, the PowerGood open drain output pulls low to indicate an output voltage out of regulation condition. The PowerGood
output can be daisy-chained to the SS/SD pin or enable pin of other controllers or converters for output voltage sequencing.
The transient comparators can be disabled by simply tying the OSNS pin to VDD.
The TPS4002x can be externally synchronized through the ILIM/SYNC pin up to 1.5× the free-running frequency. This
allows multiple contollers to be synchronized to eliminate EMI concerns due to input beat frequencies between controllers.
INTERNAL BLOCK DIAGRAM
VDD 2
OSNS 3
VDD
0.719 V
PWRGD 9
0.659 V
FB 4
0.69 V +
+
COMP 5
UVLO
OSC
RT 7
IRT
SS
ACTIVE
PWM
CLK
UVLO
PREDICTIVE
GATE
DRIVE(tm)
PWM
LOGIC
FAULT
VDD
CHARGE
PUMP
DRV
PVDD
DRV
ISS
SS/SD 6
SGND 8
SOFT
START
UVLO
CLK
SS
ACTIVE
DCHG
FAULT
COUNTER
VDD
0.28 V
CURRENT LIMIT
COMPARATOR
OC
−
+
SD
SYNC
UVLO
UVLO
VDD
IRT
1V
13 BOOT2
12 PVDD
16 BOOT1
15 HDRV
14 SW
11 LDRV
10 PGND
1 ILIM/SYNC
DISABLE
+
1.4 V
VDD
UDG−02092
2