TPS2456 Datasheet, PDF (2/31 Pages) Texas Instruments – Dual 12 V Protection / Blocking Controller

TPS2456
SLVSA78A – MARCH 2010 – REVISED MARCH 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE
TPS2456RHH
PRODUCT INFORMATION⁽¹⁾
TEMPERATURE
PACKAGE
–40°C to 85°C
QFN36 (6mm × 6mm)
MARKING
TPS2456
(1) For package and ordering information see the Package Option Addendum at the end of this document or see the TI Web site at
www.ti.com.
THERMAL INFORMATION
q_JA
q_JC(top)
q_JB
y_JT
y_JB
q_JC(bottom)
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance ⁽³⁾
Junction-to-board thermal resistance ⁽⁴⁾
Junction-to-top characterization parameter ⁽⁵⁾
Junction-to-board characterization parameter ⁽⁶⁾
Junction-to-case(bottom) thermal resistance ⁽⁷⁾
TPS2456
RHH
36 PINS
32
23
11
0.5
10
2.1
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y_JB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Over recommended junction temperature range and all voltages referenced to GND, unless otherwise noted.
PINS OR PIN GROUPS
VALUE
GAT1x, GAT2x
–0.3 to 30
INx, OUTx, SENPx, SENMx, SETx, ENx, FLTx, PGx, ORENx
–0.3 to 17
CTx, MONx
–0.3 to 5
FLTx, PGx current sinking
5
MONx current sourcing
5
VINT current
–1 to 1
Human Body Model
2
ESD
Charged Device Model
0.5
Junction Temperature
Internally Limited
UNITS
V
V
V
mA
mA
mA
kV
kV
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
2
Submit Documentation Feedback
Product Folder Link(s): TPS2456
Copyright © 2010, Texas Instruments Incorporated