TPD12S015 Datasheet, PDF (2/31 Pages) Texas Instruments – HDMI COMPANION CHIP WITH STEP-UP DC-DC, I2C LEVEL SHIFTER, AND HIGH-SPEED ESD CLAMPS FOR PORTABLE APPLICATIONS

TPD12S015
SLLSE19C – DECEMBER 2009 – REVISED NOVEMBER 2010
www.ti.com
The TPD12S015 provides a regulated 5 V output (5VOUT) for sourcing the HDMI power line. The regulated 5 V
output supplies up to 55 mA to the HDMI receiver. The control of 5VOUT and the hot plug detect (HPD) circuitry
is independent of the LS_OE control signal and is controlled by the CT_CP_HPD pin. This independent control
enables the detection scheme (5VOUT + HPD) to be active before enabling the HDMI link.
There are three non-inverting bi-directional translation circuits for the SDA, SCL, and CEC lines. Each have a
common power rail (V_CCA) on the A side from 1.1 V to 3.6V . On the B side, the SCL_B and SDA_B each have
an internal 1.75 kΩ pullup connected to the regulated 5 V rail (5VOUT). The SCL and SDA pins meet the I²C
specification and drive up to 750 pF loads. The CEC_B pin has an internal 27 kΩ pullup to an internal 3.3 V
supply.
The HPD_B port has a glitch filter to avoid false detection due to the bouncing while inserting the HDMI plug.
The TPD12S015 provides IEC61000-4-2 (Level 4) ESD protection. This device is offered in a space-saving 1.6
mm × 2.8 mm wafer-level chip scale package [WCSP (YFF)] with 0.4-mm pitch.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE^{(1) (2)}
ORDERABLE PART NUMBER
WCSP – YFF
Tape and reel
TPD12S015YFFR
TOP-SIDE MARKING
PN015
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
SYSTEM-LEVEL BLOCK DIAGRAM
HDMI Connector
Connecto
+5V P
SCL IO
SDA IO
CEC IO
HPD O
HDMI-TPD12S015-Configuration A
TPD12S015
Power Supplies
VBAT
I
I
FB
O 5VOUT(+5v)
CHDM-I5v
4.7 µH
5V DC-DC
3.3V LDO
SW
I
VCCA
I
GND A
Control Lines
CT_CP_HPD I
LS_OE I
LHDM-IVBAT
1 µH
CHDM-IVBAT
2.2µF
VBAT
VCCA
CHDM-IVCCA
0.1µF
CT_CP_HPD
LS_OE
HDMI Sink side
IO SCL_B
IO SDA_B
IO CEC_B
I HPD_B
HDMI Source side
SCL_A IO
SDA_A IO
CEC_A IO
HPD_A O
DDC-SC
DDC-SDA
CEC
HPD
CLK- I
CLk+ I
DATA 0- I
DATA 0+ I
DATA 1- I
DATA 1+ I
DATA 2- I
DATA 2+ I
I
I
I
I
I
I
I
I
+5V
CLK- _C+LK ^{D0- D0+ D1- D1+ D2- D+2}
TMDS signal
CLK-
CLK+
DATA0-
DATA 0+
DATA1-
DATA 1+
DATA2-
DATA 2+
Battery
vbat
O VBAT
PMIC
Regulator
O V1V8
Vdac_out O
uC
HDMI Sideband
P vdds_1p8
O
GPIO_HDMI-
CT_CP_HPD
O GPIO_HDMI-LS_OE
IO hdmi_scl
IO hdmi_sda
IO hdmi_cec
I hdmi_hpd
HDMI PHY
O hdmi_clkm
O hdmi_clkp
O hdmi_data0m
O hdmi_data0p
O hdmi_data1m
O hdmi_data1p
O hdmi_data2m
O hdmi_data2p
vdda_hdmi_vdac P
vssa_hdmi_vdac GND
2
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