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SN74AVCH4T245-EP Datasheet, PDF (2/14 Pages) Texas Instruments – 4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
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SN74AVCH4T245-EP
SCES771 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74AVCH4T245 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level
applied to prevent excess ICC and ICCZ.
The SN74AVCH4T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance
state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
TA
–55°C to 125°C
QFN – RSV
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
Tape and reel
CAVCH4T245MRSVREP
TOP-SIDE MARKING
SODM
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
FUNCTION TABLE(1)
(EACH 2-BIT SECTION)
CONTROL INPUTS
OE
DIR
L
L
L
H
H
X
OUTPUT CIRCUITS
A PORT B PORT
Enabled
Hi-Z
Hi-Z
Enabled
Hi-Z
Hi-Z
OPERATION
B data to A bus
A data to B bus
Isolation
(1) Input circuits of the data I/Os are always active.
LOGIC DIAGRAM (POSITIVE LOGIC) FOR 1/2 OF AVCH4T245
DIR
OE
A1
B1
A2
B2
2
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