SN74AVC4T774_3 Datasheet, PDF (2/19 Pages) Texas Instruments – 4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SN74AVC4T774
SCES693B – FEBRUARY 2008 – REVISED MAY 2008..................................................................................................................................................... www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the
direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the
B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The
input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to
prevent excess I_CC and I_CCZ.
The SN74AVC4T774 is designed so that the control pins (DIR1, DIR2, DIR3, DIR4, and OE) are supplied by
V_CCA.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V_CC isolation feature ensures that if either V_CC input is at GND, then both ports are in the high-impedance
state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CCA through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Since this device has CMOS inputs, it is very important to not allow them to float. If the inputs are not driven to
either a high V_CC state, or a low GND state, an undesirable larger than expected I_CC current may result. Since
the input voltage settlement is governed by many factors (e.g. capacitance, board-layout, package inductance,
surrounding conditions, etc.), ensuring that they these inputs are kept out of erroneous switching states and tying
them to either a high or a low level minimizes the leakage-current.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ^{(1) (2)}
ORDERABLE PART NUMBER
QFN – RGY
Tape and reel
SN74AVC4T774RGYR
QFN – RSV
Tape and reel
SN74AVC4T774RSVR
TSSOP – PW
Tube
Tape and reel
SN74AVC4T774PW
SN74AVC4T774PWR
TOP-SIDE MARKING
WT774
ZVK
WT774
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
FUNCTION TABLE
(Each Bit)
CONTROL INPUTS
OE
DIR
L
L
L
H
H
X
OUTPUT CIRCUITS
A PORT
B PORT
Enabled
Hi-Z
Hi-Z
Enabled
Hi-Z
Hi-Z
OPERATION
B data to A data
A data to B data
Isolation
LOGIC DIAGRAM (POSITIVE LOGIC)⁽¹⁾
DIR1
OE
A1
(1) Shown for a single channel
2
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B1
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