SN74AVC2T245_10 Datasheet, PDF (2/15 Pages) Texas Instruments – DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SN74AVC2T245
SCES692 – JUNE 2008...................................................................................................................................................................................................... www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74AVC2T245 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input and the output-enable (OE) activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to
the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level
applied to prevent excess I_CC and I_CCZ.
The SN74AVC2T245 is designed so that the control pins (DIR1, DIR2, and OE) are supplied by V_CCA.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V_CC isolation feature ensures that if either V_CC input is at GND, both ports are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE must be connected to V_CC through a
pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE⁽¹⁾
(EACH TRANSCEIVER)
CONTROL INPUTS
OE
DIR1
L
L
L
H
H
X
OUTPUT CIRCUITS
A PORT
B PORT
Enabled
Hi-Z
Hi-Z
Enabled
Hi-Z
Hi-Z
OPERATION
B data to A data
A data to B data
Isolation
(1) Input circuits of the data I/Os are always active.
LOGIC DIAGRAM (POSITIVE LOGIC)⁽¹⁾
DIR1
OE
A1
B1
(1) Shown for a single channel
2
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