SN74AVC126 Datasheet, PDF (2/13 Pages) Texas Instruments – QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
TERMINAL ASSIGNMENTS
D, DGV, OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 V_CC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE
A
H
H
H
L
L
X
OUTPUT
Y
H
L
Z
LOGIC SYMBOL⁽¹⁾
1
1OE
2
1A
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
EN ¹
3
1Y
6
2Y
8
3Y
11
4Y
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1OE ¹
LOGIC DIAGRAM (POSITIVE LOGIC)
3OE ¹⁰
2
1A
3
1Y
9
3A
2OE ⁴
5
2A
6
2Y
4OE ¹³
12
4A
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8
3Y
11
4Y
2