SN74AUP1T98 Datasheet, PDF (2/17 Pages) Texas Instruments – SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS

SN74AUP1T98
SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR
WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS
SCES614A – OCTOBER 2004 – REVISED SEPTEMBER 2005
www.ti.com
ORDERING INFORMATION
T_A
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
Tape and reel SN74AUP1T98YEPR
–40°C to 85°C
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Tape and reel
SN74AUP1T98YZPR
SOT (SOT-23) – DBV
Tape and reel SN74AUP1T98DBVR
SOT (SC-70) – DCK
Tape and reel SN74AUP1T98DCKR
TOP-SIDE MARKING⁽²⁾
_ _ _TK_
HT6_
TK_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION SELECTION TABLE
LOGIC FUNCTION
2-to-1 data selector
2-input AND gate
2-input OR gate with one inverted input
2-input NAND gate with one inverted input
2-input AND gate with one inverted input
2-input NOR gate with one inverted input
2-input OR gate
Inverter
Noninverted buffer
FIGURE NO.
5
6
7
7
8
8
9
10
11
Static-Power Consumption
(µA)
100%
Dynamic-Power Consumption
(pF)
100%
80%
80%
60%
40%
3.3-V
Logic^†
60%
40%
L³V^.3C^-V
Logic^†
20%
0%
AUP
20%
0%
AUP
† _{Single, dual, and triple gates}
Figure 1. AUP – The Lowest-Power Family
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2 Input
1.5
1
Output
0.5
0
−0.5 _{0 5 10 15 20 25 30 35 40 45}
Time − ns
† _{AUP1G08 data at CL = 15 pF}
Figure 2. Excellent Signal Integrity
2