SN74AUP1G125_101 Datasheet, PDF (2/24 Pages) Texas Instruments – LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

SN74AUP1G125
SCES595J – JULY 2004 – REVISED MARCH 2010
www.ti.com
This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high. This device has the input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
100%
100%
80%
80%
60%
40%
3.3-V
Logic^†
60%
40%
3.3-V
L^Lo^Vg^Cic^†
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2 ^Input
Output
1.5
1
20%
20%
0%
AUP
0%
AUP
† _{Single, dual, and triple gates}
0.5
0
−0.5
0
5
10 15 20 25 30 35 40 45
Time − ns
† _{AUP1G08 data at CL = 15 pF}
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION⁽¹⁾
T_A
PACKAGE ⁽²⁾
ORDERABLE PART NUMBER
–40°C to 85°C
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY
uQFN – DSF
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
Reel of 3000
Reel of 3000
Reel of 5000
Reel of 5000
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
SN74AUP1G125YFPR
SN74AUP1G125YZPR
SN74AUP1G125DRYR
SN74AUP1G125DSFR
SN74AUP1G125DBVR
SN74AUP1G125DBVT
SN74AUP1G125DCKR
SN74AUP1G125DCKT
SN74AUP1G125DRLR
TOP-SIDE
MARKING ⁽³⁾
_ _ _ HM _
_ _ _ HM _
HM
HM
H25_
HM_
HM_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X ⁽¹⁾
Z
(1) Floating inputs allowed.
2
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