SN74AUC125 Datasheet, PDF (2/9 Pages) Texas Instruments – QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74AUC125
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES508A – NOVEMBER 2003 – REVISED MARCH 2005
1OE ¹
2
1A
LOGIC DIAGRAM (POSITIVE LOGIC)
3OE ¹⁰
3
1Y
9
3A
2OE ⁴
5
2A
6
2Y
4OE ¹³
12
4A
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8
3Y
11
4Y
Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
V_CC
Supply voltage range
V_I
Input voltage range⁽²⁾
V_O
Voltage range applied to any output in the high-impedance or power-off state⁽²⁾
V_O
Output voltage range⁽²⁾
I_IK
Input clamp current
V_I < 0
I_OK
Output clamp current
V_O < 0
I_O
Continuous output current
Continuous current through V_CC or GND
θ_JA
Package thermal impedance⁽³⁾
T_stg
Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 V_CC + 0.5
–50
–50
±20
±100
47
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.
2