SN54LV374A Datasheet, PDF (2/18 Pages) Texas Instruments – OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54LV374A, SN74LV374A
OCTAL EDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS
WITH 3ĆSTATE OUTPUTS
SCLS408H − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
GQN PACKAGE
(TOP VIEW)
1234
A
B
C
D
E
terminal assignments
1
2
3
4
A
1Q
B
2D
OE
VCC
8Q
7D
1D
8D
C
3Q
2Q
6Q
7Q
D
4D
5D
3D
6D
E
GND
4Q
CLK
5Q
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLK D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
2
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