SN54HC273_09 Datasheet, PDF (2/20 Pages) Texas Instruments – OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

SN54HC273, SN74HC273
OCTAL DĆTYPE FLIPĆFLOPS
WITH CLEAR
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
description/ordering information (continued)
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related
directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has
no effect at the output.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR CLK D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
logic diagram (positive logic)
1D
2D
3D
3
4
7
11
CLK
4D
5D
6D
7D
8D
8
13
14
17
18
1
CLR
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
2
5
6
9
12
15
16
19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
logic diagram, each flip-flop (positive logic)
C
C
D
TG
TG
Q
C
C
C
C
TG
CLK(I)
C
TG
C
C
C
R
2
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