SLVA401A Datasheet, PDF (2/8 Pages) Texas Instruments – Power for C5504/05

C5504/05 Power Spec Table
Pin Name
LDOI ³
Voltage (V)
1.8 - 3.6
Max Current ⁴
(mA)
Tolerance
Sequencing
Order
5
Comments
Supplying ANA LDO (supplies
VDDA_ANA and VDDA_PLL).
Core
CVDD¹, CVDDRTC¹
1.05 / 1.30
500
-5%, +10%
Typical Core Power Consumption:
- 0.22mW/MHz for 75% DMAC + 25% NOP (CVDD
=1.3V @ 100MHz, Room Temp)
- 0.14mW/MHz for 75% DMAC + 25% NOP (CVDD
=1.05V @ 100MHz, Room Temp)
USB_VDD1P3, USB_VD
DA1P3
1.3V
For best performance, these voltages
70
-5%, +10%
1²
should be powered by a LDO in order to
minimize noise.
DVDDIO, DVDDRTC
1.8 / 2.5 / 2.8 /
3.3
300
-10%,
+10%
DVDDEMIF
1.8 / 2.5 / 2.8 /
3.3
245
-10%,
+10%
USB_VDDOSC,
USB_VDDA3P3,
USB_VDDPLL
3.3V
55
-5%, +5%
NOTES:
1) CVDD & CVDDRTC can be 1.05Vor 1.30V for ≤60MHz operation and 1.30V for operating higher than 60MHz
2) Power Supply Sequencing: No sequencing is required (for further details, see section 5.3.1 of the data sheet)
3) If GPAIN pins are used as general purpose outputs, the internal ANA_LDO must not be used as the max current capability of ANA_LDO
can be exceeded. In this case use an external regulator to supply VDDA_ANA..
4) This column shows the maximum design current of each power domain. See the C5505/04 data sheet for actual current consumptions of
some usage cases. See the data in the “Comments” column above.
SLVA401A