ONET2501PA Datasheet, PDF (2/8 Pages) Texas Instruments – 155-Mbps TO 2.5-Gbps LIMITING AMPLIFIER

ONET2501PA
155ĆMbps TO 2.5ĆGbps LIMITING AMPLIFIER
SLLS602A − MARCH 2004 − REVISED JULY 2004
block diagram
A simplified block diagram of the ONET2501PA is shown in Figure 1.
These compact, low power 2.5-Gbps limiting amplifiers consist of a high-speed data path with offset cancellation
block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation
block.
The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.
COC2 COC1
VCC
GND
DIN+
DIN−
+
−
Input Buffer
Bandgap Voltage
Reference and
Bias Current
Generation
Offset
Cancellation
+
−
Gain Stage
+
+
Gain Stage Gain Stage
Loss of Signal
and
RSSI Detection
+
CML
Output
Buffer
OUTPOL
VCCO
DOUT+
DOUT−
DISABLE
LOS
RSSI
TH
Figure 1. Block Diagram
high-speed data path
The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data
path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages, which provide
the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available
at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also
includes a data polarity switching function, which is controlled by the OUTPOL input, and a disable function,
controlled by the signal applied to the DISABLE input pin.
An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even
for very small input data signals.
The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.
For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be
connected to the COC1/COC2 pins.
los of signal and RSSI detection
The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block
a signal is generated, which is linear proportional to the input amplitude over a wide input voltage range. This
signal is available at the RSSI output pin.
Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means
of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of
signal is indicated at the LOS pin.
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