LP3891ES-1.2 Datasheet, PDF (2/19 Pages) Texas Instruments – 1.5% Output Accuracy (25°C), 60 nA Typical Quiescent Current in Shutdown

LP3891
SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
Figure 1. TO-220, Top View
Figure 2. DDPAK/TO-263, Top View
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BLOCK DIAGRAM
V_OUT 1
V_OUT 2
V_BIAS 3
GND 4
GND
8 N/C
7 VIN
6 S/D
5 GND
Figure 3. SO PowerPAD-8, Top View
2
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