LP3875EMP-ADJ-NOPB Datasheet, PDF (2/20 Pages) Texas Instruments – Ultra Low Dropout Voltage, Load Regulation of 0.06%

LP3875-ADJ
SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
Figure 1. TO-220-5 Package (Top View)
Bent, Staggered Leads
Figure 2. DDPAK/TO-263-5 Package (Top View)
GND
5
12 3 4
SD ^VIN ^VOUT ^ADJ
Figure 3. SOT-223-5 Package (Top View)
Table 1. PIN DESCRIPTION for TO-220-5 and DDPAK/TO-263-5 Packages
Pin #
1
2
3
4
5
Name
SD
V_IN
GND
V_OUT
ADJ
LP3875-ADJ
Shutdown
Input Supply
Ground
Output Voltage
Set Output Voltage
Function
Pin #
1
2
3
4
5
Table 2. PIN DESCRIPTION for SOT-223-5 Package
Name
SD
V_IN
V_OUT
ADJ
GND
LP3875-ADJ
Shutdown
Input Supply
Output Voltage
Set Output Voltage
Ground
Function
2
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