LP38512_15 Datasheet, PDF (2/21 Pages) Texas Instruments – 1.5A Fast-Transient Response Low-Dropout Linear Voltage Regulator with Error Flag

LP38512
SNOSAU7F – NOVEMBER 2007 – REVISED APRIL 2013
Connection Diagram
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EN 1
IN 2
GND 3
OUT 4
ERROR ⁵
TAB
IS
GND
Figure 1. Top View
DDPAK/TO-263 5 Pin Package
EN 1
IN 2
GND 3
OUT 4
ERROR 5
Exposed
DAP
Figure 2. Top View
PFM 5 Pin Package
Pin #
1
2
3
4
5
TAB/DAP
Table 1. Pin Descriptions for DDPAK/TO-263 and PFM Packages
Pin Name
EN
IN
GND
OUT
ERROR
TAB/DAP
Function
Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias
and must be tied to the input voltage, or actively driven.
Input Supply Pin
Ground
Regulated Output Voltage Pin
ERROR Flag. A high level indicates that V_OUT is within typically 15% (V_OUT falling) of the
nominal regulated voltage.
The DDPAK/TO-263 TAB, and the PFM DAP, is used as a thermal connection to remove heat
from the device to an external heatsink. The TAB/DAP is internally connected to device pin 3,
and is electrical ground connection.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings⁽¹⁾⁽²⁾
Storage Temperature Range
Soldering Temperature ⁽³⁾
ESD Rating ⁽⁴⁾
Power Dissipation⁽⁵⁾
Input Pin Voltage (Survival)
Enable Pin Voltage (Survival)
Output Pin Voltage (Survival)
ERROR Pin Voltage (Survival)
I_OUT(Survival)
DDPAK/TO-263
−65°C to +150°C
235°C, 30s
±2 kV
Internally Limited
−0.3V to +6.0V
−0.3V to +6.0V
−0.3V to +6.0V
0.3V to +6.0V
Internally Limited
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Refer to JEDEC J-STD-020C for surface mount device (SMD) package reflow profiles and conditions. Unless otherwise stated, the
temperatures and times are for Sn-Pb (STD) only.
(4) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method is per JESD22-A114.
(5) Device operation must be evaluated, and derated as needed, based on ambient temperature (T_A), power dissipation (P_D), maximum
allowable operating junction temperature (T_J(MAX)), and package thermal resistance (θ_JA).
2
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