DRV102 Datasheet, PDF (2/23 Pages) Burr-Brown (TI) – PWM SOLENOID/VALVE DRIVER

SPECIFICATIONS
At T_C = +25°C, V_S = +24V, load = series diode MUR415 and 100Ω, and 4.99kΩ Flag pull-up to +5V, unless otherwise noted.
DRV102T, F
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT
Output Saturation Voltage, Source
Current Limit
Under-Scale Current
Leakage Current
DIGITAL CONTROL INPUT⁽¹⁾
V_CTR Low (output disabled)
V_CTR High (output enabled)
I_CTR Low (output disabled)
I_CTR High (output enabled)
Propagation Delay: On-to-Off
Off-to-On
DELAY TO PWM⁽³⁾
Delay Equation⁽⁴⁾
Delay Time
Minimum Delay Time⁽⁵⁾
DUTY CYCLE ADJUST
Duty Cycle Range
Duty Cycle Accuracy
vs Supply Voltage
Nonlinearity⁽⁶⁾
DYNAMIC RESPONSE
Output Voltage Rise Time
Output Voltage Fall Time
Oscillator Frequency
FLAG
Normal Operation
Fault⁽⁷⁾
Sink Current
Under-Current Flag: Set
Reset
Over-Current Flag: Set
Reset
THERMAL SHUTDOWN
Junction Temperature
Shutdown
Reset from Shutdown
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
TEMPERATURE RANGE
Specified Range
Storage Range
Thermal Resistance, θ_JC
7-Lead DDPAK, 7-Lead TO-220
Thermal Resistance, θ_JA
7-Lead DDPAK, 7-Lead TO-220
I_O = 1A
I_O = 0.1A
Output Transistor Off, V_S = +60V, V_O = 0V
V_CTR = 0V
V_CTR = +5V
dc to PWM Mode
C_D = 0.1µF
C_D = 0
49% Duty Cycle, R_PWM = 25.5kΩ
49% Duty Cycle, V_S = 8V to 60V
20% to 80% Duty Cycle
V_O = 10% to 90% of V_S
V_O = 90% to 10% of V_S
20kΩ Pull-Up to +5V, I_O < 1.5A
Sinking 1mA
V_FLAG = 0.4V
I_O = 0
No Heat Sink
+1.7
+2.2
+1.3
+1.7
2
2.7
3.4
16
±0.01
±2
0
+2.2
–80⁽²⁾
20⁽²⁾
0.9
1.8
+1.2
V_S
Delay to PWM ≈ C_D • 10⁶ (C_D in F)
80
97
110
15
10 to 90
±1
±7
±1
±5
±2
0.25
2.5
0.25
2.5
19
24
29
+4
+4.9
+0.2
+0.4
2
5.2
11
5.2
11.5
V
V
A
mA
mA
V
V
µA
µA
µs
µs
s
ms
µs
%
%
%
% FSR
µs
µs
kHz
V
V
mA
µs
µs
µs
µs
+165
°C
+150
°C
+24
V
+8
+60
V
6.5
9
mA
–55
+125
°C
–55
+125
°C
3
°C/W
65
°C/W
NOTES: (1) Logic high enables output (normal operation). (2) Negative conventional current flows out of the terminals. (3) Constant dc output to PWM (pulse-width
modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust pin low corresponds to an infinite (continuous) delay.
(5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) V_IN at pin 3 to percent of duty cycle at pin 6. (7) A fault results from over-temperature,
over-current, or under-current conditions.
2
DRV102
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SBVS009A