CDC3RL02 Datasheet, PDF (2/15 Pages) Texas Instruments – LOW PHASE-NOISE TWO-CHANNEL CLOCK FAN-OUT BUFFER

CDC3RL02
SCHS371 – NOVEMBER 2009
www.ti.com
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE^{(1) (2)}
ORDERABLE PART NUMBER TOP-SIDE MARKING⁽³⁾
NanoStar™ WCSP – YFP
Tape and reel
CDC3RL02YFPR
___4L_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ● = Pb-free).
NO.
NAME
A1
V_BATT
A2
CLK_OUT1
B1
V_LDO
B2
CLK_REQ1
C1
MCLK_IN
C2
CLK_REQ2
D1
GND
D2
CLK_OUT2
TERMINAL FUNCTIONS
I/O
DESCRIPTION
I
Input to internal LDO
O
Clock output 1
O
1.8 V I/O supply for CDC3RL02 and external TCXO
I
Clock request from peripheral 2
I
Master clock input
I
Clock request from peripheral 1
–
Ground
O
Clock output 2
CLK_REQ1
L
L
H
H
Table 2. FUNCTION TABLE
INPUTS
CLK_REQ2
L
H
L
H
MCLK_IN
X
CLK
CLK
CLK
OUTPUTS
CLK_OUT1 CLK_OUT2
L
L
L
CLK
CLK
L
CLK
CLK
V_BATT
LOGIC DIAGRAM
LDO
V_LDO
GND
V_CC
EN
CLK_OUT1
CLK_REQ1
MCLK_IN
V_CC
EN
CLK_OUT2
CLK_REQ2
Switch/
Decoder
2
Submit Documentation Feedback
Product Folder Link(s): CDC3RL02
Copyright © 2009, Texas Instruments Incorporated