CDC319 Datasheet, PDF (2/11 Pages) Texas Instruments – 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I²C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
FUNCTION TABLE
INPUTS
OUTPUTS
OE
A
1Y0–1Y3
2Y0–2Y3
3Y0–3Y1
L
X
Hi-Z
Hi-Z
Hi-Z
H
L
L
L
L
H
H
H†
H†
H†
† _{The function table assumes that all outputs are enabled via the appropriate I2C}
configuration register bit. If the output is disabled via the appropriate configuration bit,
then the output is driven to a low state, regardless of the state of the A input.
logic diagram (positive logic)
20
OE
14
SDATA
I2C
10
I2C
Register
/
Space
15
SCLOCK
9
A
2, 3, 6, 7
1Y0–1Y3
22, 23, 26, 27
2Y0–2Y3
11, 18
3Y0 – 3Y1
TERMINAL
NAME
NO.
1Y0–1Y3
2, 3, 6, 7
2Y0–2Y3
22, 23, 26, 27
3Y0–3Y1
11, 18
A
9
OE
20
SCLOCK
15
SDATA
14
GND
VCC
4, 8, 12, 16,
17, 21, 25
1, 5, 10, 13,
19, 24, 28
Terminal Functions
I/O
DESCRIPTION
O 3.3-V SDRAM byte 0 clock outputs
O 3.3-V SDRAM byte 1 clock outputs
O 3.3-V clock outputs provided for feedback control of external PLLs (phase-locked loops)
I
Clock input
Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal
I
140-kΩ pullup resistor is internally integrated.
I
I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated.
I/O
Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally
integrated.
Ground
3.3-V power supply
2
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