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CD54HCT175 Datasheet, PDF (2/12 Pages) Texas Instruments – High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset
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CD54HC175, CD74HC175, CD54HCT175, CD74HCT175
Functional Diagram
4
D0
9
CP
1
MR
5
D1
12
D2
13
D3
D
2
Q
Q0
CP
3
R
Q
Q0
D
7
Q
Q1
CP
6
R
Q
Q1
D
10
Q
Q2
CP
11
R
Q
Q2
D
15
Q
Q3
CP
14
R
Q
Q3
TRUTH TABLE
INPUTS
OUTPUTS
RESET (MR)
CLOCK CP
DATA Dn
Qn
Qn
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level,
Q0 = Level Before the Indicated Steady-State Input Conditions Were Established.
Logic Diagram
4 (5, 12, 13)
D
Dn
CL
p
n
CL
CL
p
n
CL
R
1
MR
9
CP
CL
p
n
CL
CL
CP
ONE OF FOUR F/F
CL
p
n
CL CL
3( 6, 11, 14)
Qn
2( 7, 10, 15)
Qn
TO OTHER THREE F/F
TO OTHER THREE F/F
8 16
GND VCC
2
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