CD54HC4015_08 Datasheet, PDF (2/11 Pages) Texas Instruments – High Speed CMOS Logic Dual 4-Stage Static Shift Register

Functional Diagram
CD54HC4015, CD74HC4015
7
1D
9
1CP
6
1MR
5
1Q₀
4
1Q₁
3
1Q₂
10
1Q₃
15
2D
1
2CP
14
2MR
13
2Q₀
12
2Q₁
11
2Q₂
2
2Q₃
GND = 8
V_CC = 16
TRUTH TABLE
INPUTS
OUTPUTS
CP
D
↑
l
↑
h
↓
X
X
X
R
Q₀
Q₁
Q₂
Q₃
L
L
q’₀
q’₁
q’₂
L
H
q’₀
q’₁
q’₂
L
q’₀
q’₁
q’₂
q’₃
H
L
L
L
L
H = High Voltage Level
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
X = Don’t Care.
↑ = Low to High Clock Transition
↓ = High to Low Clock Transition
q’_n = Lower case letters indicate the state of the referenced output one set-up time prior to the Low to
High clock transition.
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