CD54HC40103_08 Datasheet, PDF (2/16 Pages) Texas Instruments – High-Speed CMOS Logic 8-Stage Synchronous Down Counters

Pinout
CD54HC40103, CD74HC40103, CD74HCT40103
CD54HC40103
(CERDIP)
CD74HC40103, CD74HCT40103
(PDIP, SOIC)
TOP VIEW
CP 1
MR 2
TE 3
P0 4
P1 5
P2 6
P3 7
GND 8
16 V_CC
15 PE (SYNC)
14 TC
13 P7
12 P6
11 P5
10 P4
9 PL (ASYNC)
Functional Diagram
14
P7
13
12 ^P6
11 ^P5
10 ^P4
7 ^P3
6 ^P2
5 ^P1
P0
4
15 9 3 1 2
16 8
TRUTH TABLE
CONTROL INPUTS
MR
PL
PE
TE
PRESET MODE
ACTION
1
1
1
1
Synchronous
Inhibit Counter
1
1
1
0
Count Down
1
1
0
X
Preset On Next Positive Clock Transition
1
0
X
X
Asynchronously Preset Asychronously
0
X
X
X
Clear to Maximum Count
1 = High Level.
0 = Low Level.
X = Don’t Care.
Clock connected to clock input.
Synchronous Operation: changes occur on negative-to-positive clock transitions.
Load Inputs: MSB = P7, LSB = P0.
2