CD54AC164 Datasheet, PDF (2/13 Pages) Intersil Corporation – 8-Bit Serial-In/Parallel-Out Shift Registers

Functional Diagram
CD54/74AC164, CD54/74ACT164
1
DS1
2
DS2
98
MR
CP
3
Q0
4
Q1
5
Q2
6
Q3
10
Q4
11
Q5
12
Q6
13
Q7
GND = 7
V_CC = 14
MODE SELECT - TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
MR
CP
DS1
DS2
Q0
Q1 - Q7
RESET (CLEAR)
L
X
X
X
L
L-L
SHIFT
H
↑
l
l
L
q0 - q6
H
↑
l
h
L
q0 - q6
H
↑
h
l
L
q0 - q6
H
↑
h
h
H
q0 - q6
H = HIGH voltage level steady state.
L = LOW voltage level steady state.
h = HIGH voltage level one setup time prior to the LOW-to_HIGH clock transition.
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
X = Don’t care.
q = Lowercase letters indicate the state of the referenced output prior to the LOW-to-HIGH clock transition.
↑ = LOW-to-HIGH clock transition.
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