BQ29441 Datasheet, PDF (2/17 Pages) Texas Instruments – Voltage Protection for 2-Series, 3-Series, or 4-Series Cell Li-Ion Batteries

bq29440, bq2944L0
bq29441, bq29442, bq29443, bq29449, bq2944L9
SLUSA15C – JUNE 2010 – REVISED NOVEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
T_A
–40°C
to
+110°C
PART
NUMBER
BQ29440
BQ2944L0
BQ29441
BQ29442
BQ29443
BQ29449
BQ2944L9
OUT PIN
LATCH
OPTION
No
Yes
No
No
No
No
Yes
Table 1. ORDERING INFORMATION⁽¹⁾
PACKAGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
OVP
QFN-8
DRB
440
44L0
441
442
443
449
44L9
4.35 V
4.35 V
4.40 V
4.45 V
4.50 V
4.30 V
4.30 V
ORDERING INFORMATION⁽²⁾
TAPE AND REEL TAPE AND REEL
(LARGE) ⁽³⁾
(SMALL) ⁽⁴⁾
BQ29440DRBR
BQ29440DRBT
BQ2944L0DRBR BQ2944L0DRBT
BQ29441DRBR
BQ29441DRBT
BQ29442DRBR
BQ29442DRBT
BQ29443DRBR
BQ29443DRBT
BQ29449DRBR
BQ29449DRBT
BQ2944L9DRBR BQ2944L9DRBT
(1) Example: bq2944L0DRBR is a device with the OUT latch option with a V_OV threshold of 4.35 V.
Contact Texas Instruments for other V_OV threshold options.
(2) For the most current package and ordering information, see the Package Addendum at the end of this document, or the TI website at
www.ti.com.
(3) Large tape and reel quantity is 3,000 units.
(4) Small tape and reel quantity is 250 units.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
q_JA
q_JC(top)
q_JB
y_JT
y_JB
q_JC(bottom)
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case(bottom) thermal resistance⁽⁷⁾
bq2944x
DRB
8 PINS
50.5
25.1
19.3
0.7
18.9
5.2
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
PIN FUNCTIONS
PIN NAME PIN NO.
DESCRIPTION
CD
6
Connection to external capacitor for programmable delay time
GND
4
Ground pin
OUT
8
Output
VC1
1
Sense voltage input for top cell
VC2
2
Sense voltage input for second-to-top cell
VC3
3
Sense voltage input for third-to-top cell
VC4
5
Sense voltage input for fourth-to-top cell (bottom cell)
VDD
7
Power supply
2
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq29440 bq2944L0 bq29441 bq29442 bq29443 bq29449 bq2944L9