ADC101S021CIMF Datasheet, PDF (2/23 Pages) Texas Instruments – ADC101S021 Single Channel, 50 to 200 ksps, 10-Bit A/D Converter

ADC101S021
SNAS307F – JULY 2005 – REVISED MARCH 2013
Connection Diagram
V_A 1
6 CS
GND 2 ^ADC101S021 5 SDATA
V_{IN 3}
4 SCLK
Figure 1. 6-Lead SOT-23 or WSON
See DBV or NGF Package
Block Diagram
V_IN
T/H
10-BIT
SUCCESSIVE
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ADC
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CONTROL
LOGIC
SCLK
CS
SDATA
Pin No.
Symbol
ANALOG I/O
3
V_IN
DIGITAL I/O
4
SCLK
5
SDATA
6
CS
POWER SUPPLY
1
2
PAD
V_A
GND
GND
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Description
Analog input. This signal can range from 0V to V_A.
Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins.
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to
GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin.
The ground return for the supply and signals.
For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground.
2
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