PCI7621 Datasheet, PDF (195/298 Pages) Texas Instruments – DUAL SINGLE SOCKET CARDBUS AND ILTRAMEDIA CONTROLLER WITH INTEGRATED 1304-A - CONTROLLER WITH DEDICATED FLASH MEDIA SOCKET

8.18 Self-ID Count Register
The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID
packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8−12 for a complete description
of the register contents.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Self-ID count
Type
RU R
R
R
R
R
R
R RU RU RU RU RU RU RU RU
Default X
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Self-ID count
Type
R
R
R
R
R RU RU RU RU RU RU RU RU RU R
R
Default 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
31
30−24
23−16
15−11
10−2
1−0
Register:
Offset:
Type:
Default:
Self-ID count
68h
Read/Update, Read-only
X0XX 0000h
Table 8−12. Self-ID Count Register Description
FIELD NAME
selfIDError
RSVD
selfIDGeneration
RSVD
selfIDSize
RSVD
TYPE
RU
R
RU
R
RU
R
DESCRIPTION
When bit 31 is set to 1, an error was detected during the most recent self-ID packet reception. The
contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no
errors are detected. Note that an error can be a hardware error or a host bus write error.
Reserved. Bits 30−24 return 0s when read.
The value in this field increments each time a bus reset is detected. This field rolls over to 0 after
reaching 255.
Reserved. Bits 15−11 return 0s when read.
This field indicates the number of quadlets that have been written into the self-ID buffer for the current
bits 23−16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field
is cleared to 0s when the self-ID reception begins.
Reserved. Bits 1 and 0 return 0s when read.
8−15