AM3359_15 Datasheet, PDF (191/248 Pages) Texas Instruments – AM335x Sitara Processors

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SPRS717H – OCTOBER 2011 – REVISED MAY 2015
7.8 I²C
For more information, see the Inter-Integrated Circuit (I²C) section of the AM335x Sitara Processors
Technical Reference Manual (SPRUH73).
7.8.1 I²C Electrical Data and Timing
Table 7-68. I²C Timing Conditions – Slave Mode
PARAMETER
Output Condition
C_b
Capacitive load for each bus line
STANDARD MODE
MIN
MAX
400
FAST MODE
UNIT
MIN
MAX
400 pF
Table 7-69. Timing Requirements for I²C Input Timings
(see Figure 7-68)
STANDARD MODE
FAST MODE
NO.
UNIT
MIN
MAX
MIN
MAX
1 t_c(SCL)
Cycle time, SCL
10
2 t_{su(SCLH-SDAL)}
Setup time, SCL high before SDA low (for a repeated
START condition)
4.7
2.5
µs
0.6
µs
3 t_h(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
4
0.6
µs
4 t_w(SCLL)
5 t_w(SCLH)
6 t_{su(SDAV-SCLH)}
7 t_h(SCLL-SDAV)
8 t_w(SDAH)
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
Pulse duration, SDA high between STOP and START
conditions
4.7
4
250
0⁽²⁾
3.45⁽³⁾
4.7
1.3
0.6
100⁽¹⁾
0⁽²⁾
1.3
µs
µs
ns
0.9⁽³⁾ µs
µs
9 t_r(SDA)
Rise time, SDA
1000
300 ns
10 t_r(SCL)
Rise time, SCL
1000
300 ns
11 t_f(SDA)
Fall time, SDA
300
300 ns
12 t_f(SCL)
Fall time, SCL
300
300 ns
13 t_{su(SCLH-SDAH)}
Setup time, high before SDA high (for STOP condition)
4
0.6
µs
14 t_w(SP)
Pulse duration, spike (must be suppressed)
0
50
0
50 ns
(1) A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW
period of the SCL signal, it must output the next data bit to the SDA line t_{r max} + t_su(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the
standard-mode I²C-Bus Specification) before the SCL line is released.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum t_h(SDA-SCLL) has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.
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