UCC28500 Datasheet, PDF (19/31 Pages) Texas Instruments – BICMOS PFC/PWM COMBINATION CONTROLLER

UCC28500, UCC28501, UCC28502, UCC28503
UCC38500, UCC38501, UCC38502, UCC38503
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
TYPICAL APPLICATION
CP
Rf
CZ
RI
−
+
CAOUT
Figure 10. Current Loop Compensation
voltage loop
The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic
of the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple
at the input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate
the contribution of this ripple to the total harmonic distortion of the system (refer to Figure 11).
VOUT
Cf
Rf
CZ
RIN
−
RD
+
VREF
Figure 11. Voltage Amplifier Configuration
The gain of the voltage amplifier, G_VA, can be determined by first calculating the amount of peak ripple present
on the output capacitor V_OPK. The peak value of the second harmonic voltage is given by equation (23), where
f_R is the frequency of the rectified line voltage. For this design f_R is equal to 120 Hz.
V_OPK + _{ǒ2 p}
f_R
P_IN
C_BOOST
V_BOOST^Ǔ
(23)
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