TPS62736_15 Datasheet, PDF (19/37 Pages) Texas Instruments – TPS6273x Programmable Output Voltage Ultra-Low Power Buck Converter With Up to 50 mA / 200 mA Output Current

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TPS62736, TPS62737
SLVSBO4C – OCTOBER 2012 – REVISED DECEMBER 2014
Feature Description (continued)
the voltage on VIN reaches the UVLO condition. The UVLO level is continuously monitored. The buck regulator
continues to operate in pass (100% duty cycle) mode, passing the input voltage to the output, as long as VIN is
greater than UVLO and less than VIN minus I_OUT times R_DS(on) of the high-side FET (that is, VIN – I_OUT x R_DS(on)-
HS^{). In order to save power from being dissipated through other ICs on this supply rail while allowing for a faster}
wake up time, the buck regulator can be enabled and disabled through the EN2 pin for systems that desire to
completely turn off the regulated output.
9.3.2 Programming OUT Regulation Voltage and VIN_OK
To set the proper output-regulation voltage and input voltage power-good comparator, the external resistors must
be carefully selected. Figure 62 illustrates an application diagram which uses the minimal resistor count for
setting both VOUT and VIN_OK. Note that VBIAS is nominally 1.21 V per the electrical specification table.
Referring to Figure 52, the OUT DC set point is given by Equation 1.
VOUT
=
æ
VBIAS _ç
è
R₁ + R₂ + R₃
R₁ + R₂
ö
÷
ø
(1)
The VIN_OK setting is given by Equation 2.
VIN _
OK
=
æ
VBIAS _ç
R₁
+
R₂
+
R₃
ö
÷
è
R₁
ø
(2)
The sum of the resistors is recommended to be no greater than 13 MΩ, that is, RSUM = R1 + R2 + R3 = 13 MΩ.
Due to the sampling operation of the output resistors, lowering RSUM only increases quiescent current slightly as
can be seen in Figure 22. Higher resistors may result in poor output voltage regulation and/or input voltage
power-good threshold accuracies due to noise pickup through the high-impedance pins or reduction of effective
resistance due to parasitic resistance created from board assembly residue. See Layout for more details.
If it is preferred to separate the VOUT and VIN_OK resistor strings, two separate strings of resistors could be
used as shown in Figure 62. The OUT DC set point is then given by Equation 3.
VOUT
=
æ
VBIAS _ç
R₃
+
R₄
ö
÷
è ^R4 ø
(3)
The VIN_OK setting is then given by Equation 4.
VIN _
OK
=
æ
VBIAS _ç
R₁
+
R₂
ö
÷
è ^R1 ø
(4)
If it is preferred to disable the VIN_OK setting, the VIN_OK_SET pin can be tied to VIN. To set VOUT in this
configuration, use Equation 3. To tighten the DC set point accuracy, use external resistors with better than 1%
resistor tolerance. Because output voltage ripple has a large effect on input line regulation and the output load
regulation, using a larger output capacitor will improve both line and load regulation.
9.3.3 Nano-Power Management and Efficiency
The high efficiency of the TPS6273x is achieved through the proprietary Nano-Power management circuitry and
algorithm. This feature essentially samples and holds all references in order to reduce the average quiescent
current. That is, the internal circuitry is only active for a short period of time and then off for the remaining period
of time at the lowest feasible duty cycle. A portion of this feature can be observed in Figure 66 where the VRDIV
node is monitored. Here, the VRDIV node provides a connection to the input (larger voltage level) and generates
the output reference (lower-voltage level) for a short period of time. The divided down value of input voltage is
compared to VBIAS and the output voltage reference is sampled and held to get the VOUT_SET point.
Because this biases a resistor string, the current through these resistors is only active when the Nano-Power
management circuitry makes the connection — hence, reducing the overall quiescent current due to the
resistors. This process repeats every 64 ms. Similarly, the VIN_OK level is monitored every 64 ms, as shown in
Figure 55.
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