TPS54218_15 Datasheet, PDF (19/40 Pages) Texas Instruments – TPS54218 2.95-V to 6-V Input, 2-A Output, 2-MHz , Synchronous Step-Down Switcher With Integrated FETs (SWIFT™)

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Device Functional Modes (continued)
COMP
R3
C2 ^R3
C1
C1
TPS54218
SLVS974C – SEPTEMBER 2009 – REVISED DECEMBER 2014
g_M(ea)
+
C_OUT(ea)
5 pF
R_OUT(ea)
V_OUT
R1
VSENSE
V_REF
R2
Type IIB
Type IIA
Figure 34. Types of Frequency Compensation
The design guidelines for TPS54218 device loop compensation are as follows:
1. Calculate the modulator pole (f_P(MOD)) and the esr zero, (f_Z1 using Equation 11 and Equation 12. If the output
voltage is a high percentage of the capacitor rating it may be necessary to derate the output capacitor
(C_OUT). Use the capacitor manufacturer information to derate the capacitor value. Use Equation 13 and
Equation 14 to estimate a starting point for the crossover frequency, f_C. Equation 13 shows the geometric
mean of the modulator pole and the ESR zero and Equation 14 is the mean of modulator pole and the
switching frequency. Use the lower value of Equation 13 or Equation 14 as the maximum crossover
frequency.
f_P(mod)
=
I_{OUT(max )}
2p ´ V_OUT ´ C_OUT
(11)
1
f_Z(mod) = _{2p ´ RESR ´ COUT}
(12)
f_C = f _{P(mod) ´}f _Z(mod)
(13)
f_C =
f_P(mod)
´
f
SW
2
(14)
2. Calculate resistor R3. Equation 15 shows the calculation for resistor R3.
R3 = ^{2p ´ fC ´ VOUT ´ COUT}
g_M(ea) ´ V_REF ´ g_M(ps)
where
• g_M(ea) is the amplifier gain (225 μA/V)
• g_M(ps) is the power stage gain (13 A/V)
(15)
3. Place a compensation zero at the dominant pole. f_P. Equation 16 shows the calculation for capacitor C1.
1
f_P = _{COUT ´ RLOAD ´ 2p}
(16)
C1 = ^{RL ´ COUT}
R3
(17)
4. Capacitor C2 is optional. It can be used to cancel the zero from the output capacitor (C_OUT) ESR.
C2 = ^{RESR ´ COUT}
R3
(18)
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