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| TPS40170-Q1_15 Datasheet, PDF (19/51 Pages) Texas Instruments – TPS40170-Q1 4.5-V to 60-V, Wide-Input, Synchronous PWM Buck Controller | |||
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Feature Description (continued)
Internal Logic RUN
tCAL
TPS40170-Q1
SLVSB90B â JANUARY 2012 â REVISED DECEMBER 2014
Clamped at VDD
SS
0.5 V
0.65 V
VSS
tSS
VVALLEY
1.1 V
SS_EAMP
VREF = 0.6 V
VCOMP
(2)
(1)
VOUT
t â Time
Figure 21. Soft-Start Waveforms
UDG-09203
Referring to Figure 21:
NOTE
(1) VREF dominates the positive input of the error amplifier.
(2) SS_EAMP dominates the positive input of the error amplifier.
For 0 < VSS_EAMP < VREF
(R1+ R2)
VOUT = VSS(EAMP) ´
R2
(8)
For VSS_EAMP > VREF
(R1+ R2)
VOUT = VREF ´ R2
(9)
7.3.7.1 Soft-Start During Overcurrent Fault
The soft-start block also has a role to control the fault-logic timing. If an overcurrent fault (OC_FAULT) is
declared, the soft-start capacitor is discharged internally through the device by a small current ISS(sink) (1.05 µA,
typical). Once the SS pin capacitor is discharged to below VSS(flt,low) (300 mV, typical), the soft-start capacitor
begins charging again. If the fault is persistent, a fault is declared which is determined by the overcurrent-
protection state machine. If the soft-start capacitor is below VSS(flt,high) (2.5 V, typical), then the soft-start capacitor
continues to charge until it reaches VSS(flt,high) before a discharge cycle is initiated. This ensures that the re-start
time-interval is always constant. Figure 22 shows the restart timing.
Copyright © 2012â2014, Texas Instruments Incorporated
Product Folder Links: TPS40170-Q1
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