TLV62150ARGTR Datasheet, PDF (19/34 Pages) Texas Instruments – 4-17V 1A Step-Down Converter with DCS-Control

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PVIN
SW
AVIN
VOS
EN
PG
TLV62150
SS/TR
FB
DEF
AGND
FSW
PGND
TLV62150, TLV62150A
SLVSB71B – FEBRUARY 2012 – REVISED JUNE 2013
VOUT1
PVIN
SW
AVIN
VOS
R1
EN
PG
TLV62150
SS/TR
FB
R2
DEF
AGND
FSW
PGND
VOUT2
Figure 37. Sequence for Ratiometric and Simultaneous Startup
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as
VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start
up sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft
start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing
circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.8V, the output voltage accuracy may have a wider
tolerance than specified.
Output Filter And Loop Stability
The TLV62150 is internally compensated to be stable with L-C filter combinations corresponding to a corner
frequency to be calculated with Equation 12:
f _LC
=
2p
1
L×C
(12)
Proven nominal values for inductance and ceramic capacitance are given in Table 1 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which will be affected. More
information including a detailed L-C stability matrix can be found in SLVA463.
The TLV62150 includes an internal 25pF feedforward capacitor, connected between the VOS and FB pins. This
capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of the
feedback divider, per equation Equation 13 and Equation 14:
spacing
1
f _zero = _{2p × R1 × 25 pF}
(13)
spacing
f _pole
=
2p
1
× 25 pF
×
ççèæ
1
R₁
+
1
R₂
÷÷øö
(14)
spacing
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