TLV320AIC11 Datasheet, PDF (19/55 Pages) Texas Instruments – General-Purpose Low-Voltage 1.1V to 3.6V/0 16-bit 22-KSPS DSP CODEC

2.1.5 Antialiasing Filter
The built-in antialiasing filter has a 3-dB cutoff frequency of 70 kHz.
2.1.6 Sigma-Delta ADC
The sigma-delta analog-to-digital converter is a sigma-delta modulator with 128× oversampling. The ADC provides
high-resolution, low-noise performance using oversampling techniques. Due to the oversampling employed, only
single-pole RC filters are required on the analog inputs.
2.1.7 Decimation Filter
The decimation filters reduce the digital data rate to the sampling rate. This is accomplished by decimating with a ratio
of 1:64. The output of the decimation filter is a 16-bit 2s-complement data word clocking at the sample rate selected
for that particular data channel. The BW of the filter is 0.45 × FS and scales linearly with the sample rate.
2.1.8 Sigma-Delta DAC
The sigma-delta digital-to-analog converter is a sigma-delta modulator with 128× oversampling. The DAC provides
high-resolution, low-noise performance using oversampling techniques.
2.1.9 Interpolation Filter
The interpolation filter resamples the digital data at a rate of 64 times the incoming sample rate. The high-speed data
output from the interpolation filter is then used in the sigma-delta DAC. The BW of the filter is 0.45 x FS and scales
linearly with the sample rate.
2.1.10 Analog and Digital Loopback
The analog and digital loopbacks provide a means of testing the modem data ADC/DAC channels and can be used
for in-circuit system level tests. The analog loopback routes the DAC low-pass filter output into the analog input where
it is then converted by the ADC to a digital word. The digital loopback routes the ADC output to the DAC input on the
device. Analog loopback is enabled by writing 01 to bits D7 and D6 respectively in control register 3. Digital loopback
is enabled by writing 10 to bits D7 and D6 in control register 3 (see Appendix A).
2.1.11 FIR Overflow Flag
The decimator FIR filter sets an overflow flag (bit D7) in control register 1 to indicate that the input analog signal has
exceeded the range of the internal decimation-filter calculations. When the FIR overflow flag has been set in the
register, it remains set until the register is read by the user. Reading this value resets the overflow flag.
If FIR overflow occurs, the input signal has to be attenuated either by the PGA or some other method.
2.1.12 Bypass Mode
An option is provided to bypass the FIR filter sections of the decimation and interpolation filters. This mode is selected
through bits D1 and D2 of control register 1, and effectively increases the frequency of FS signal to 4 times the normal
FIR-filter output rate. The sinc filters of the two paths can not be bypassed.
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